1. Field of the Invention
The present invention generally relates to low power dynamic random access memories (DRAMs) and, more particularly, to an improved fault-tolerant design for a DRAM.
2. Background Description
There is a strong demand for low power DRAMs, especially with a low standby current. One design concern of the low power DRAMs is a word-line and bit-line short. Conventional redundancy architecture employs a repair region in each block. This architecture has several disadvantages. First, each block must have at least one, and preferably two, redundant row and column, increasing design space. Second, grouped or clustered fails are difficult to repair. Third, a cross fail (i.e., a word-line, bit-line short-circuit) increases the standby current, causing a standby failure. One approach to minimizing current flow in the even of a cross fail is the use of a pulsed equalizer control while enabling the precharge equalizer signal. This scheme, however allows a floating state in each bit-line pair, causing a bit-line voltage drift in a long pause condition. To avoid this problem, a reference cell is provided for bit-line sensing. Such a reference cell, however, requires a complicated layout, difficult control and a large active current dissipation.